Verilog

Logical operations

Logical Negation      !
Logical AND          &&
Logical OR           ||
Logical Equality     ==
Logical Inequality   != 

Bitwise operations

Bitwise Negation      ~
Bitwise AND           &  
Bitwise Inclusive OR  | 
Bitwise Exclusive OR  ^
Bitwise Equivalence  ~^, ^~ 

Shifts

8'h12 << 4 = 8'h20
8'h12 >> 4 = 8'h01

Replication {n{}}

{4{2'b01}} = 8'b01010101

Concatenation {,}

{2'b01, 4'hF, 1'b1, 1'b0} = 8'b01111110

Literals

Base         Symbol   Legal Values
binary       b or B   0, 1, x, X, z, Z, ?, _  
octal        o or O   0-7, x, X, z, Z, ?, _  
decimal      d or D   0-9, _  
hexadecimal  h or H   0-9, a-f, A-F, x, X, z, Z, ?, _

Examples
8'b11111111    = 255
32'hBAADF00D   = 3 131 961 357

Arrays

reg [3:0] name [31:0];

The above describes an array of 32 Elements each, 4 bits wide which can be assigned via behavioral Verilog code.

Blocks

Block statements are used to group statements together. XST only supports sequential blocks. Within these blocks, the statements are executed in the order listed. Parallel blocks are not supported by XST. Block statements are designated by begin and end keywords, and are discussed within examples later in this chapter.

Modules

In Verilog a design component is represented by a module. The connections between components are specified within module instantiation statements. Such a statement specifies an instance of a module. Each module instantiation statement must be given a name (instance name). In addition to the name, a module instantiation statement contains an association list that specifies which actual nets or ports are associated with which local ports (formals) of the module declaration.

All procedural statements occur in blocks that are defined inside modules. There are two kinds of procedural blocks: the initial block and the always block. Within each block, Verilog uses a begin and end to enclose the statements. Since initial blocks are ignored during synthesis, only always blocks are discussed. Always blocks usually take the following format:

always 
  begin 
  statement 
  ... 
end 

where each statement is a procedural assignment line terminated by a semicolon.

Testbench

reg clk;

initial    // clock generation
begin
  clk = 0;
  forever #10 clk = ~clk;
end 

initial
begin
    @(posedge clk);
    while(value==0) @(posedge clk);
    repeat(100) @(posedge clk);

    $stop;
    $finish;
end