Difference between revisions of "STM32F103 Microcontroller"

Revision as of 13:08, 25 October 2010

STM32F103RET6 block diagram

Key features of the STM32F103RET6 microcontroller

Documents and files

• http://www.st.com/mcu/familiesdocs-110.html
• Reference Manual
• Specifications
• Programming Manual
• Keil µVision 4.12
• Flash Loader Demonstrator
• Futurlec STM32 Stamp product page

Power saving levels

1. Sleep mode (Cortex-M3 core stopped, peripherals kept running)
2. Stop mode (all clocks are stopped)
3. Standby mode (1.8V domain powered-off)

Clocks

STM32F103RET6 clock tree

HSI (8 MHz internal RC oscillator)
HSE (8 MHz external crystal oscillator)
LSI (40 kHz internal RC - watchdog, RTCCLK)
LSE (32768 Hz external crystal (RTCCLK))

PLLCLK  - Output from PLL, 8-64 MHz in 4 MHz steps, 72-128 MHz in 8 MHz steps
SYSCLK  - PLLCLK, HSI or HSE
AHBCLK  - SYSCLK / AHB prescaler (this clock has no name in the datasheet, except AHB peripheral clock)
PCLK1   - AHBCLK / APB1 prescaler - APB1 bus (max 36 MHz)
PCLK2   - AHBCLK / APB2 prescaler - APB2 bus (max 72 MHz)
USBCLK  - PLLCLK / USB prescaler
I2SCLK  - SYSCLK
SDIOCLK - AHBCLK
FSMCCLK - AHBCLK
FCLK    - AHBCLK
ADCCLK  - AHBCLK / (APB2 prescaler * ADC prescaler)

The MCO pin (PA8) can output one of SYSCLK, HSI, HSE, PLLCLK / 2
When the HSI is the PLL clock input, maximum system clock frequency is 64 MHz.
The SDIO AHB interface is clocked with a fixed frequency equal to AHBCLK / 2.
If the APB prescaler is 1, timers run at PCLK else at 2 * PCLK

Flash memory

• 0-24 MHz - zero wait state
• 24-48 MHz - one wait state
• 48-72 MHz - two wait states

The prefetch buffer must be switched on/off only when SYSCLOCK is lower than 24 MHz.

Pins with special functions

PA9  ----------> ICL3232
PA10 <--|100R|-- ICL3232
PB2  - Boot1 22 kOhm to +3.3 V or Gnd
PC14 - 32 kHz crystal
PC15 - 32 kHz crystal
PD0  - 8 MHz crystal
PD1  - 8 MHz crystal

The JTAG pins are in input PU/PD after reset:
 PA15: JTDI in PU
 PA14: JTCK in PD
 PA13: JTMS in PU
 PB4: NJTRST in PU

Peripherials

64 kB SRAM, 512 kB FLASH
3 x 12 bit A/D converters
2 x 12 bit D/A converters
5 x USART
2 x Advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on 6 channels.
4 x General purpose timer TIM2, TIM3, TIM4 and TIM5 - 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 16 input captures / output compares / PWMs 
2 x Basic timer TIM6 and TIM7 - These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.
3 x SPI
2 x I2S (multiplexed on SPI pins)
2 × I2C
1 x SD card interface 1/4/8 bit
1 x USB full speed
1 x CAN network interface
1 x CRC (cyclic redundancy check) calculation unit
1 x 24 bit systick timer
1 x RTC (real-time clock) and backup registers
2 x DMA controller, 5 + 7 channels
1 x Temperature sensor

A/D converters

• ADC1_IN17 is connected to V_REFINT 1.2 V (1.16 V - 1.24 V)
• ADC1_IN16 is connected to the Temperature sensor
• ADC2_IN16 and ADC2_IN17 are connected to V_SS
• ADC3_IN9, ADC3_IN14, ADC3_IN15, ADC3_IN16 and ADC3_IN17 are connected to V_SS

The recommended sampling time for the internal channels is 17.1 μs. The TSVREFE bit must be set to enable both internal channels.

Timers

Flash uploader

Command line parameters for STMFlashLoader.exe:

   -c  --pn 3 --br 115200 --db 8 --sb 1 --to 1000 -i "STM32_High-density_512K" -e --all -d --fn "#H" --v

--pn 3 indicates com port: COM3

Important things to remember

• Registers need a clock to latch the data, so enable all the the upstream clocks before trying to configure a peripheral
• Pins with special functions

Pinout

Programming

Registers

• note [y:x] refers to all bits in a register from bit x to bit y (inclusive)