Difference between revisions of "Arty S7"
From ScienceZero
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* 256 MB DDR3L memory and 16 MB Quad-SPI Flash | * 256 MB DDR3L memory and 16 MB Quad-SPI Flash | ||
| − | |||
* Programmable from JTAG and Quad-SPI flash | * Programmable from JTAG and Quad-SPI flash | ||
* 100 MHz & 12MHz external clocks | * 100 MHz & 12MHz external clocks | ||
Revision as of 06:03, 18 December 2018
- 256 MB DDR3L memory and 16 MB Quad-SPI Flash
- Programmable from JTAG and Quad-SPI flash
- 100 MHz & 12MHz external clocks
- Internal ADC Dual-channel, 1 MSPS
- Powered from USB or any 7V-15V source
- Interaction and Sensory Devices
- 4 Switches
- 4 Buttons
- 1 Board Reset Button
- 1 FPGA Reset Button
- 4 Green LEDs
- 2 RGB LEDs
- Expansion Connectors:
- 4 Pmod connectors
- Arduino/chipKIT Shield connector
| XC7S50-1CSGA324C | XC7S25-1CSGA324 | |
|---|---|---|
| Logic Slices | 8150 | 3650 |
| 6-Input LUTs | 32 600 | 14 600 |
| Flip-Flops | 65 200 | 29 200 |
| Block RAM | 75 * 4500 = 337.5 KByte | 45 * 4500 = 202.5 KByte |
| DSP Slices | 120 | 80 |
| Clock resources | 5 PLLs | 3 PLLs |
DSP48E1 slice
- 25-bit pre-adder with D register to enhance the capabilities of the A path
- INMODE control supports balanced pipelining when dynamically switching between multiply (A*B) and add operations (A:B)
- 25 x 18 multiplier
- 30-bit A input of which the lower 25 bits feed the A input of the multiplier, and the entire 30-bit input forms the upper 30 bits of the 48-bit A:B concatenate internal bus.
- Cascading A and B input
- Semi-independently selectable pipelining between direct and cascade paths
- Separate clock enables two-deep A and B set of input registers
- Independent C input and C register with independent reset and clock enable.
- CARRYCASCIN and CARRYCASCOUT internal cascade signals to support 96-bit accumulators/adders/subtracters in two DSP48E1 slices
- MULTSIGNIN and MULTSIGNOUT internal cascade signals with special OPMODE setting to support a 96-bit MACC extension
- Single Instruction Multiple Data (SIMD) Mode for three-input adder/subtracter which precludes use of multiplier in first stage
- Dual 24-bit SIMD adder/subtracter/accumulator with two separate CARRYOUT signals
- Quad 12-bit SIMD adder/subtracter/accumulator with four separate CARRYOUT signals
- 48-bit logic unit
- Bitwise logic operations – two-input AND, OR, NOT, NAND, NOR, XOR, and XNOR
- Logic unit mode dynamically selectable via ALUMODE
- Pattern detector
- Overflow/underflow support
- Convergent rounding support
- Terminal count detection support and auto resetting
- Cascading 48-bit P bus supports internal low-power adder cascade
- The 48-bit P bus allows for 12-bit/QUAD or 24-bit/DUAL SIMD adder cascade support
- Optional 17-bit right shift to enable wider multiplier implementation
- Dynamic user-controlled operating modes
- 7-bit OPMODE control bus provides X, Y, and Z multiplexer select signals
- Carry in for the second stage adder
- Support for rounding
- Support for wider add/subtracts
- 3-bit CARRYINSEL multiplexer
- Carry out for the second stage adder
- Support for wider add/subtracts
- Available for each SIMD adder (up to four)
- Cascaded CARRYCASCOUT and MULTSIGNOUT allows for MACC extensions up to 96 bits
- Optional input, pipeline, and output/accumulate registers
- Optional control registers for control signals (OPMODE, ALUMODE, and CARRYINSEL)
- Independent clock enable and resets for greater flexibility, with reset having priority.
- To save power when the first stage multiplier is not being used, the USE_MULT attribute allows the customer to gate off internal multiplier logic.
