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A16 - High Performance 16 bit RISC CPU
  • Harvard style architecture that executes all instructions in a single clock cycle.
  • 8 registers, the program counter is mapped to register 8.
  • Conditional execution of all instructions.
  • Condition flags are set on demand.
  • All instructions execute in a single clock cycle.
  • Branch-link instruction where the program counter is copied to R6.


Schematics (4400x2056):
a16t.gif (7901 bytes)

Emulator and assembler (a16 emulator.zip 19 KB)

 

Arithmetic and logical
opcode<cond|s> Rd, Rb, (Ra|#exp)
#exp has a range of 0-15  (0-7 when <cond> is specified)
Rd can't be PC when <s> is specified
Opcode Name Operation Flags Affected
ADD Add Rd = Rb + Ra Z C
SUB Subtract Rd = Rb - Ra Z C
AND Bitwise AND Rd = Rb AND Ra Z
ORR Bitwise OR Register Rd = Rb OR Ra Z
EOR Bitwise Exclusive-OR Rd = Rb EOR Ra Z

 

Move
opcode<cond> Rd,  (Ra|#exp)
#exp has a range of -256 to 255 (-64 to 63 when <cond> is specified)
Opcode Name Operation Flags Affected
MOV Move Rd =  Ra Z
MOV Move Rd =  #exp -

 

Comparison
opcode Rd,  (Ra|#exp)
#exp has a range of 0-15
Opcode Name Operation Flags Affected
CMN Compare Negative Rd + Ra Z C
CMP Compare Rd - Ra Z C
TST Test Rd AND Ra Z
TOR Test OR Rd OR Ra Z
TEQ Test Equivalence Rd EOR Ra Z

 

Load/store
opcode<cond|s>  Rd,  (Ra,#exp)
#exp has a range of 0-15 (0-7 when <cond> is specified)
Opcode Name Operation Flags Affected
LDR Load Register Rd = [Ra] Z
STR Store Register [Ra] = Rd Z

 

Branching and program flow
opcode<cond> label
label has a range of 0-2047 (0-511 when <cond> is specified)
Opcode Name Operation
B Branch PC = label
BL Branch Link R6 = PC, PC = label
RET Return PC = R6 + 1
SKP Skip next instruction PC = PC + 2

 

Shifting
opcode<cond|s> Rd, Ra
Opcode Name Operation Flags Affected
LSL Logical Shift Left Rd = Ra << 1 Z C
LSR Logical Shift Right Rd = Ra >> 1 Z C
ROR Rotate Right Rd = Ra[0] -> (Ra >> 1) Z C
SWP Swap Rd = (Ra << 8) OR (Ra >> 8) Z
SWM Swap Mask Rd = (Ra >> 8) and 255 Z