Difference between revisions of "STM32 Oscilloscope"

Revision as of 20:46, 11 May 2010

Features

Vertical (Voltage/Frequency)

V/Div
AC/DC
Offset
Invert
Probe divider / multiplier

Horizontal (Time)

T/Div
Offset

Trigger

Voltage level trigger
Trigger on rising / falling edge
Single trigger / force trigger / trigger continiously
Auto detect and track trigger level
Trigger at fixed frequency / Trigger output
External trigger
Pretrigger (sample continiously then stop n samples after the trigger)
Filtered trigger (low frequency / high frequency / number of pulses)
Video trigger
RS-232 trigger

Auto Scale

Voltage
Period

Metered values

Voltage
True RMS
Average
Peak
Peak to peak
Frequency
Duty

Markers

Voltage
t1
t2
delta t
frequency

Data output

Save display snapshot to picture
Save display frames for movie
Save wave data to file (raw / .CSV)
Stream non interrupted wave data to file

Display modes

Waveform

range (old oscilloscope method)

Average per sample

Average per waveform

XYZ
Fourier transform

Spectrum

Average spectrum

Subtract average

Spectrogram

Turtle - Channel A = speed, Channel B = direction
TV (pixel brightness)
Histogram
Roll mode (continuous scrolling)

BPM mode for heart rate monitoring

wide range of scroll rates

dynamically zoom in to check on activity of extremely slow rates

Dynamically labelled grid

Pause and scroll back

Protocol decoding

RS-232
TTL RS-232
IR remotes
I2C
SPI

DSP

Pre-scale before process
Add channels
Subtract channels
Multiply channels
AM demod
FM demod
Configurable bandpass filtering
Phase tracking hum removal
Audio output

Log playback

Output and control interfaces

Computer via RS232
Computer via Wireless RS232
LCD touch screen
Computer via USB

Logic analyzer

Multichannel

Component value testing

Coding

Limits

The A/D converter is 12 bits
Maximum guaranteed clock frequency is 14 MHz, giving 1 MHz sample rate
Maximum possible with a 8 MHz crystal is 12 MHz
Two ADCs can be run in interleave for (12 / 14) * 2 = 1.74 MHz (highest guaranteed sample rate)
Maximum ADC clock rate at 72 MHz system clock is 36 MHz giving (12 / 14) * 2 = 5.14 MHz
Maximum system clock is 128 MHz giving a theoretical maximum of 9.14 MHz by overclocking everything

Protocol

One byte each:
C SS DDD...
C = Code
S = Size
D = Data

Commands PC → STM32

0 0 4 DDDD - Set sample rate in Hz
1 0 5 D DDDD - Trigger mode & voltage
2 0 1 D - Input type 0=DC, 1=AC, 3=frequency
3 0 4 DD.DD - Input gain
4 0 1 D - Number of channels
5 0 2 DD - Set pin state of a 16 pin port
6 0 0 - Reset
7 0 4 AAAA - Read data from address
8 0 8 AAAA DDDD - Write data to address
9 0 4 AAAA - Execute address

Commands STM32 → PC

0 SS HL HL... - Sample data, 8 bit unsigned, H = highest value during the sample period, L = lowest value during the sample period
1 SS DD DD... - Sample data, 16 bit per sample
2 SS DD DD... - Pin state from one 16 pin port
3 0 4 DDDD - Return data from address

Advanced features for the future

Realtime view and control over IP by another computer
iPad/IPhone view and control
Web interface

@@ Line 102: / Line 102: @@
 ==Coding==
+===Limits===
+*The A/D converter is 12 bits
+*Maximum guaranteed clock frequency is 14 MHz, giving 1 MHz sample rate
+*Maximum possible with a 8 MHz crystal is 12 MHz
+*Two ADCs can be run in interleave for (12 / 14) * 2 = 1.74 MHz (highest guaranteed sample rate)
+*Maximum ADC clock rate at 72 MHz system clock is 36 MHz giving (12 / 14) * 2 = 5.14 MHz
+*Maximum system clock is 128 MHz giving a theoretical maximum of 9.14 MHz by overclocking everything
 ===Protocol===
   One byte each: