Difference between revisions of "Raspberry Pi 3"
From ScienceZero
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== CPU == | == CPU == | ||
| − | 4 | + | 4 × ARM Cortex A53 |
| + | *8-stage pipelined processor with 2-way superscalar, in-order execution pipeline | ||
| + | *DSP and NEON SIMD extensions are mandatory per core | ||
| + | *VFPv4 Floating Point Unit onboard (per core) | ||
| + | *Hardware virtualization support | ||
| + | *TrustZone security extensions | ||
| + | *64-byte cache lines | ||
| + | *10-entry L1 TLB, and 512-entry L2 TLB | ||
| + | *4 KiB conditional branch predictor, 256-entry indirect branch predictor | ||
| + | |||
| + | AArch64 features[edit] | ||
| + | *New instruction set, A64 | ||
| + | *Has 31 general-purpose 64-bit registers. | ||
| + | *Has dedicated zero or stack pointer (SP) register (depending on instruction). | ||
| + | *The program counter (PC) is no longer directly accessible as a register. | ||
| + | *Instructions are still 32 bits long and mostly the same as A32 (with LDM/STM instructions and most conditional execution dropped). | ||
| + | *Has paired loads/stores (in place of LDM/STM). | ||
| + | *No predication for most instructions (except branches). | ||
| + | *Most instructions can take 32-bit or 64-bit arguments. | ||
| + | *Addresses assumed to be 64-bit. | ||
| + | *Advanced SIMD (NEON) enhanced | ||
| + | *Has 32 × 128-bit registers (up from 16), also accessible via VFPv4. | ||
| + | *IEEE 754 compliant double-precision floating point. | ||
| + | *AES encrypt/decrypt and SHA-1/SHA-2 hashing instructions also use these registers. | ||
== Bare metal programming== | == Bare metal programming== | ||
* http://arm.flatassembler.net/ | * http://arm.flatassembler.net/ | ||
Revision as of 08:54, 28 August 2017
- Quad Core 1.2GHz Broadcom BCM2837 64bit CPU
- 1GB RAM
- BCM43438 wireless LAN and Bluetooth Low Energy (BLE) on board
- 40-pin extended GPIO
- 4 USB 2 ports
- 4 Pole stereo output and composite video port
- Full size HDMI
- CSI camera port for connecting a Raspberry Pi camera
- DSI display port for connecting a Raspberry Pi touchscreen display
CPU
4 × ARM Cortex A53
- 8-stage pipelined processor with 2-way superscalar, in-order execution pipeline
- DSP and NEON SIMD extensions are mandatory per core
- VFPv4 Floating Point Unit onboard (per core)
- Hardware virtualization support
- TrustZone security extensions
- 64-byte cache lines
- 10-entry L1 TLB, and 512-entry L2 TLB
- 4 KiB conditional branch predictor, 256-entry indirect branch predictor
AArch64 features[edit]
- New instruction set, A64
- Has 31 general-purpose 64-bit registers.
- Has dedicated zero or stack pointer (SP) register (depending on instruction).
- The program counter (PC) is no longer directly accessible as a register.
- Instructions are still 32 bits long and mostly the same as A32 (with LDM/STM instructions and most conditional execution dropped).
- Has paired loads/stores (in place of LDM/STM).
- No predication for most instructions (except branches).
- Most instructions can take 32-bit or 64-bit arguments.
- Addresses assumed to be 64-bit.
- Advanced SIMD (NEON) enhanced
- Has 32 × 128-bit registers (up from 16), also accessible via VFPv4.
- IEEE 754 compliant double-precision floating point.
- AES encrypt/decrypt and SHA-1/SHA-2 hashing instructions also use these registers.
