Difference between revisions of "RP2040"
From ScienceZero
Line 1: | Line 1: | ||
+ | = Programmable input/output block (PIO) = | ||
+ | There are two PIO blocks with four state machines each, that can independently execute sequential programs to manipulate GPIOs and transfer data. Unlike a general purpose | ||
+ | processor, PIO state machines are highly specialised for IO, with a focus on determinism, precise timing, and close integration with fixed-function hardware. Each state machine is equipped with: | ||
+ | * Two 32-bit shift registers – either direction, any shift count | ||
+ | * Two 32-bit scratch registers | ||
+ | * 4×32-bit bus FIFO in each direction (TX/RX), reconfigurable as 8×32 in a single direction | ||
+ | * Fractional clock divider (16 integer, 8 fractional bits) | ||
+ | * Flexible GPIO mapping | ||
+ | * DMA interface, sustained throughput up to 1 word per clock from system DMA | ||
+ | * IRQ flag set/clear/status | ||
+ | |||
== Instruction set == | == Instruction set == | ||
+ | Alle PIO instructions are 16 bits long and execute in a single cycle with no pipeline. | ||
Bit: 15-13 | 12 11 10 9 8 | 7 6 5 | 4 3 2 1 0 | Bit: 15-13 | 12 11 10 9 8 | 7 6 5 | 4 3 2 1 0 |
Revision as of 14:04, 9 August 2022
Programmable input/output block (PIO)
There are two PIO blocks with four state machines each, that can independently execute sequential programs to manipulate GPIOs and transfer data. Unlike a general purpose processor, PIO state machines are highly specialised for IO, with a focus on determinism, precise timing, and close integration with fixed-function hardware. Each state machine is equipped with:
- Two 32-bit shift registers – either direction, any shift count
- Two 32-bit scratch registers
- 4×32-bit bus FIFO in each direction (TX/RX), reconfigurable as 8×32 in a single direction
- Fractional clock divider (16 integer, 8 fractional bits)
- Flexible GPIO mapping
- DMA interface, sustained throughput up to 1 word per clock from system DMA
- IRQ flag set/clear/status
Instruction set
Alle PIO instructions are 16 bits long and execute in a single cycle with no pipeline.
Bit: 15-13 | 12 11 10 9 8 | 7 6 5 | 4 3 2 1 0 JMP 0 0 0 | Delay/side-set | Condition | Address WAIT 0 0 1 | Delay/side-set | Pol|Source | Index IN 0 1 0 | Delay/side-set | Source | Bit-count OUT 0 1 1 | Delay/side-set | Destination | Bit-count PUSH 1 0 0 | Delay/side-set | 0| IfF |Blk | 0 0 0 0 0 PULL 1 0 0 | Delay/side-set | 1| IfE |Blk | 0 0 0 0 0 MOV 1 0 1 | Delay/side-set | Destination | Op | Source IRQ 1 1 0 | Delay/side-set | 0|Clr|Wait | Index SET 1 1 1 | Delay/side-set | Destination | Data