Difference between revisions of "RP2040"
From ScienceZero
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= Single-cycle IO block (SIO) = | = Single-cycle IO block (SIO) = | ||
Peripherals that require low-latency, deterministic access | Peripherals that require low-latency, deterministic access | ||
+ | == CPUID == | ||
+ | Core 0 reads a value of 0 when accessing this registe, and core 1 reads a value of 1 | ||
== Integer Divider == | == Integer Divider == | ||
== Interpolator == | == Interpolator == | ||
== Inter-processor FIFOs == | == Inter-processor FIFOs == | ||
== Hardware Spinlocks == | == Hardware Spinlocks == | ||
− | |||
= DMA = | = DMA = |
Revision as of 21:34, 10 August 2022
Contents
Single-cycle IO block (SIO)
Peripherals that require low-latency, deterministic access
CPUID
Core 0 reads a value of 0 when accessing this registe, and core 1 reads a value of 1
Integer Divider
Interpolator
Inter-processor FIFOs
Hardware Spinlocks
DMA
CRC
Types of checksum:
- CRC-32, MSB-first and LSB-first
- CRC-16-CCITT, MSB-first and LSB-first
- Simple summation (add to 32-bit accumulator)
- Even parity
Types of processing of the resut:
- Bit inversion
- Bit reversal
- Byte swap
Memory
- A 16kB read-only memory (ROM) is at address 0x00000000
- Off-chip execute-in-place (XIP) flash interface (2MB on Raspberry Pi Pico) at address 0x10000000
- Four 16k x 32-bit banks of SRAM (64kB each)
- Word striped at 0x20000000
- Non striped at 0x21000000, 0x21010000, 0x21020000 and 0x21030000
- Two 1k x 32-bit banks of SRAM (4kB each) at 0x20040000 and 0x20041000
- If flash XIP caching is disabled, the cache becomes available as 16kB SRAM starting at 0x15000000
- If the USB is not used, the USB data DPRAM can be used as a 4kB memory starting at 0x50100000
Programmable input/output block (PIO)
There are two PIO blocks with four state machines each, that can independently execute sequential programs to manipulate GPIOs and transfer data. Unlike a general purpose processor, PIO state machines are highly specialised for IO, with a focus on determinism, precise timing, and close integration with fixed-function hardware. Each state machine is equipped with:
- Two 32-bit shift registers – either direction, any shift count
- Two 32-bit scratch registers
- 4×32-bit bus FIFO in each direction (TX/RX), reconfigurable as 8×32 in a single direction
- Fractional clock divider (16 integer, 8 fractional bits)
- Flexible GPIO mapping
- DMA interface, sustained throughput up to 1 word per clock from system DMA
- IRQ flag set/clear/status
Instruction set
All PIO instructions are 16 bits long and execute in a single cycle with no pipeline.
Bit: 15-13 | 12 11 10 9 8 | 7 6 5 | 4 3 2 1 0 JMP 0 0 0 | Delay/side-set | Condition | Address WAIT 0 0 1 | Delay/side-set | Pol|Source | Index IN 0 1 0 | Delay/side-set | Source | Bit-count OUT 0 1 1 | Delay/side-set | Destination | Bit-count PUSH 1 0 0 | Delay/side-set | 0| IfF |Blk | 0 0 0 0 0 PULL 1 0 0 | Delay/side-set | 1| IfE |Blk | 0 0 0 0 0 MOV 1 0 1 | Delay/side-set | Destination | Op | Source IRQ 1 1 0 | Delay/side-set | 0|Clr|Wait | Index SET 1 1 1 | Delay/side-set | Destination | Data