Instruction set: ARM

Description key

Field	Description
<>	Optional
(x|y)	Either x or y but not both
#exp	Constant expression or label
Rn	one of R0-R15, LR, SP or PC
B	Byte transfer.
T	Force address translation from a privileged mode. (Not pre-index!)
!	Update Rn after use
S	Set condition codes
{Rlist}	Any combination of registers.
^	If R15 is in {Rlist} then update PSR.

Integer instructions (32 bit)

Shift types

shift	Description
ASL (Rn|#exp)	Arithmetic shift (LSL is preferred).
LSL (Rn|#exp)	Logical shift left.
ASR (Rn|#exp)	Arithmetic shift right.
LSR (Rn|#exp)	Logical shift right.
ROR (Rn|#exp)	Rotate right.
RRX	Rotate right one bit with extend. LSB -> C, C -> MSB

Prosessor Status Register (PSR)

Flag	Description
N	Negative flag
Z	Zero flag
C	Carry flag
V	Overflow flag
I	Interrupt request disable
F	Fast interrupt request disable

Condition codes

cond	Description	Condition
AL	Always (normally omitted)	Any
CC	Carry clear	C=0
CS	Carry set	C=1
EQ	Equal	Z=1
GE	Greater than or equal	N=V
GT	Greater than	N=V and Z=0
HI	Higher (unsigned)	C=1 and Z=0
LE	Less than or equal	N<>V or Z=1
LS	Lower or same (unsigned)	C=0 or Z=1
LT	Less than	N<>V
MI	Negative	N=1
NE	Not equal	Z=0
NV	Never (do not use)	N/A
PL	Positive	N=0
VC	Overflow clear	V=0
VS	Overflow set	V=1
LO	Lower (unsigned)	Same as CC
HS	Higher/same (unsigned)	Same as CS

Arithmetic and logical instructions

mnemonic<cond><S> Rd,<Rn>,(#exp|Rm<,shift>)
#exp has a range of X ROR N*2 where X=0-255 and N=0-15

mnemonic	Description	Operation
ADC	Add with carry	Rd=Rn+Rm+C
ADD	Add	Rd=Rn+Rm
SBC	Subtract with carry	Rd=Rn-Rm-(1-C)
SUB	Subtract	Rd=Rn-Rm
RSC	Reverse subtract with carry	Rd=Rm-Rn-(1-C)
RSB	Reverse subtract	Rd=Rm-Rn
AND	Bitwise AND	Rd=Rn AND Rm
BIC	Bitwise AND NOT	Rd=Rn AND (NOT Rm)
ORR	Bitwise OR Register	Rd=Rn OR Rm
EOR	Bitwise EOR	Rd=Rn EOR Rm
MOV	Move	Rd=Rm
MVN	Move NOT	Rd=NOT Rm

Comparisons

mnemonic<cond><S|P> Rn,(#exp|Rm<,shift>)
#exp has a range of X ROR N*2 where X=0-255 and N=0-15

mnemonic	Description	Operation
CMN	Compare	Rn+Rm
CMP	Compare	Rn-Rm
TEQ	Test equal	Rn EOR Rm
TST	Test	Rn AND Rm

Multiply instructions

mnemonic<cond><S> Rd,Rm,Rs
mnemonic<cond><S> Rd,Rm,Rs,Rn

mnemonic	Description	Operation
MUL	Multiply	Rd=Rm*Rs
MLA	Multiply-accumulate	Rd=Rm*Rs+Rn

Branching instructions

mnemonic<cond> #exp #exp has a range of +-2²³

mnemonic	Description	Operation
B	Branch	PC = PC + expression
BL	Branch and link	R14 = PC + 4 & PSR, PC = PC + expression

Single register load/store instructions

mnemonic<cond><B><T> Rd,(address|#exp)
#exp has a range of +-4095 bytes.

mnemonic	Description	Operation
LDR	Load Register
STR	Store Register

address (pre-index)	address (post-index)
[Rn]	N/A
[Rn, #exp]<!>	[Rn], #exp
[Rn, <->Rm]<!>	[Rn], <->Rm
[Rn, <->Rm, shift #s]<!>	[Rn], <->Rm, shift #s

Multiple register load/store instructions

mnemonic<cond>type Rn<!>,{Rlist}<^>

mnemonic	Description	Operation
LDM	Load Registerlist
STM	Store Registerlist

type	Block load/store	type	Stack pop	type	Stack push
IA	Increment Rn After	FD	Full Descending stack	EA	Empty Ascending stack
IB	Increment Rn Before	ED	Empty Descending stack	FA	Full Ascending stack
DA	Decrement Rn After	FA	Full Ascending stack	ED	Empty Descending stack
DB	decrement Rn Before	EA	Empty Ascending stack	FD	Full Descending stack

SWI instruction

mnemonic<cond> #exp
#exp has a range of 0-2²⁴

mnemonic	Description	Operation
SWI	Software interrupt	Jumps to the SWI vector

Thumb instructions (16 bit)

Field	Updates	Action
MOV Rd, #<immed>	N Z	Rd := immed
MOV Rd, Rm	N Z * *	Rd := Rm
MOV Rd, Rm		Rd := Rm
CPY Rd, Rm		Rd := Rm
ADD Rd, Rn, #<immed>	N Z C V	Rd := Rn + immed
ADD Rd, Rn, Rm	N Z C V	Rd := Rn + Rm
ADD Rd, Rm		Rd := Rd + Rm
ADD Rd, #<immed>	N Z C V	Rd := Rd + immed
ADC Rd, Rm	N Z C V	Rd := Rd + Rm + C-bit
ADD SP, #<immed>		R13 := R13 + immed
ADD Rd, SP, #<immed>		Rd := R13 + immed
ADD Rd, PC, #<immed>		Rd := (R15 AND 0xFFFFFFFC) + immed
SUB Rd, Rn, Rm	N Z C V	Rd := Rn – Rm
SUB Rd, Rn, #<immed>	N Z C V	Rd := Rn – immed
SUB Rd, #<immed>	N Z C V	Rd := Rd – immed
SBC Rd, Rm	N Z C V	Rd := Rd – Rm – NOT C-bit
SUB SP, #<immed>		R13 := R13 – immed
NEG Rd, Rm	N Z C V	Rd := – Rm
MUL Rd, Rm	N Z * *	Rd := Rm * Rd
CMP Rn, Rm	N Z C V	update CPSR flags on Rn – Rm
CMN Rn, Rm	N Z C V	update CPSR flags on Rn + Rm
CMP Rn, #<immed>	N Z C V	update CPSR flags on Rn – immed
NOP		None
AND Rd, Rm	N Z	Rd := Rd AND Rm
EOR Rd, Rm	N Z	Rd := Rd EOR Rm
ORR Rd, Rm	N Z	Rd := Rd OR Rm
BIC Rd, Rm	N Z	Rd := Rd AND NOT Rm
MVN Rd, Rm	N Z	Rd := NOT Rm
TST Rn, Rm	N Z	update CPSR flags on Rn AND Rm
LSL Rd, Rm, #<shift>	N Z C*	Rd := Rm << shift
LSL Rd, Rs	N Z C*	Rd := Rd << Rs[7:0]
LSR Rd, Rm, #<shift>	N Z C	Rd := Rm >> shift
LSR Rd, Rs	N Z C	Rd := Rd >> Rs[7:0]
ASR Rd, Rm, #<shift>	N Z C	Rd := Rm ASR shift
ASR Rd, Rs	N Z C*	Rd := Rd ASR Rs[7:0]
ROR Rd, Rs	N Z C*	Rd := Rd ROR Rs[7:0]
REV Rd, Rm		Rd[31:24] := Rm[7:0], Rd[23:16] := Rm[15:8], Rd[15:8] := Rm[23:16], Rd[7:0] := Rm[31:24]
REV16 Rd, Rm		Rd[15:8] := Rm[7:0], Rd[7:0] := Rm[15:8], Rd[31:24] := Rm[23:16], Rd[23:16] := Rm[31:
REVSH Rd, Rm		Rd[15:8] := Rm[7:0], Rd[7:0] := Rm[15:8], Rd[31:16] := Rm[7] * &FFFF
LDR Rd, [Rn, #<immed>]		Rd := [Rn + immed]
LDRH Rd, [Rn, #<immed>]		Rd := ZeroExtend([Rn + immed][15:0])
LDRB Rd, [Rn, #<immed>]		Rd := ZeroExtend([Rn + immed][7:0])
LDR Rd, [Rn, Rm]		Rd := [Rn + Rm]
LDRH Rd, [Rn, Rm]		Rd := ZeroExtend([Rn + Rm][15:0])
LDRSH Rd, [Rn, Rm]		Rd := SignExtend([Rn + Rm][15:0])
LDRB Rd, [Rn, Rm]		Rd := ZeroExtend([Rn + Rm][7:0])
LDRSB Rd, [Rn, Rm]		Rd := SignExtend([Rn + Rm][7:0])
LDR Rd, [PC, #<immed>]		Rd := [(R15 AND 0xFFFFFFFC) + immed]
LDR Rd, [SP, #<immed>]		Rd := [R13 + immed]
LDMIA Rn!, <reglist>		Loads list of registers
STR Rd, [Rn, #<immed>]		[Rn + immed] := Rd
STRH Rd, [Rn, #<immed>]		[Rn + immed][15:0] := Rd[15:0]
STRB Rd, [Rn, #<immed>]		[Rn + immed][7:0] := Rd[7:0]
STR Rd, [Rn, Rm]		[Rn + Rm] := Rd
STRH Rd, [Rn, Rm]		[Rn + Rm][15:0] := Rd[15:0]
STRB Rd, [Rn, Rm]		[Rn + Rm][7:0] := Rd[7:0]
STR Rd, [SP, #<immed>]		[R13 + immed] := Rd
STMIA Rn!, <reglist>		Stores list of registers
PUSH <loreglist>		Push registers onto stack
PUSH <loreglist+LR>		Push LR and registers onto stack
POP <loreglist>		Pop registers from stack
POP <loreglist+PC>		Pop registers, branch to address loaded to PC
POP <loreglist+PC>		Pop, branch, and change to ARM state if address[0] = 0
B{cond} label		R15 := label
B label		R15 := label
BL label		R14 := address of next instruction, R15 := label
BX Rm		R15 := Rm AND 0xFFFFFFFE
BLX label		R14 := address of next instruction, R15 := label Change to ARM
BLX Rm		R14 := address of next instruction, R15 := Rm AND 0xFFFFFFFE
SXTH Rd, Rm		Rd[31:0] := SignExtend(Rm[15:0])
SXTB Rd, Rm		Rd[31:0] := SignExtend(Rm[7:0])
UXTH Rd, Rm		Rd[31:0] := ZeroExtend(Rm[15:0])
UXTB Rd, Rm		Rd[31:0] := ZeroExtend(Rm[7:0])
SWI <immed_8>		Software interrupt processor exception
CPSID <iflags>		Disable specified interrups
CPSIE <iflags>		Enable specified interrups
SETEND <endianness>		Sets endianness for loads and saves.
BKPT <immed_8>		Prefetch abort or enter debug state

Vector Floating Point Instruction Set

Instruction	Exceptions	Action
FMUL<S/D>{cond} Fd, Fn, Fm	IO, OF, UF, IX	Fd := Fn * Fm
FNMUL<S/D>{cond} Fd, Fn, Fm	IO, OF, UF, IX	Fd := - (Fn * Fm)
FMAC<S/D>{cond} Fd, Fn, Fm	IO, OF, UF, IX	Fd := Fd + (Fn * Fm)
FNMAC<S/D>{cond} Fd, Fn, Fm	IO, OF, UF, IX	Fd := Fd - (Fn * Fm)
FMSC<S/D>{cond} Fd, Fn, Fm	IO, OF, UF, IX	Fd := - Fd + (Fn * Fm)
FNMSC<S/D>{cond} Fd, Fn, Fm	IO, OF, UF, IX	Fd := - Fd - (Fn * Fm)
FADD<S/D>{cond} Fd, Fn, Fm	IO, OF, IX	Fd := Fn + Fm
FSUB<S/D>{cond} Fd, Fn, Fm	IO, OF, IX	Fd := Fn - Fm
FDIV<S/D>{cond} Fd, Fn, Fm	IO, DZ, OF, UF, IX	Fd := Fn / Fm
FCPY<S/D>{cond} Fd, Fm		Fd := Fm
FABS<S/D>{cond} Fd, Fm		Fd := abs(Fm)
FNEG<S/D>{cond} Fd, Fm		Fd := - Fm
FSQRT<S/D>{cond} Fd, Fm	IO, IX	Fd := sqrt(Fm)
FCMP{E}<S/D>{cond} Fd, Fm	IO	Set FPSCR flags on Fd - Fm
FCMP{E}Z<S/D>{cond} Fd	IO	Set FPSCR flags on Fd - 0
FCVTDS{cond} Dd, Sm	IO	Dd := convertStoD(Sm)
FCVTSD{cond} Sd, Dm	IO, OF, UF, IX	Sd := convertDtoS(Dm)
FUITO<S/D>{cond} Fd, Sm	IX	Fd := convertUItoF(Sm)
FSITO<S/D>{cond} Fd, Sm	IX	Fd := convertSItoF(Sm)
FTOUI{Z}<S/D>{cond} Sd, Fm	IO, IX	Sd := convertFtoUI(Fm)
FTOSI{Z}<S/D>{cond} Sd, Fm	IO, IX	Sd := convertFtoSI(Fm)
FST<S/D>{cond} Fd, [Rn{, #<immed>}]		[address] := Fd. Immediate range 0-1020, multiple of 4.
FSTMIA<S/D/X>{cond} Rn, <VFPregs>		Saves list of VFP registers, starting at address in Rn.
FSTMIA<S/D/X>{cond} Rn!, <VFPregs>		synonym: FSTMEA (empty ascending)
FSTMDB<S/D/X>{cond} Rn!, <VFPregs>		synonym: FSTMFD (full descending)
FLD<S/D>{cond} Fd, [Rn{, #<immed>}]		Fd := [address]. Immediate range 0-1020, multiple of 4.
FLDMIA<S/D/X>{cond} Rn, <VFPregs>		Loads list of VFP registers, starting at address in Rn.
FLDMIA<S/D/X>{cond} Rn!, <VFPregs>		synonym: FLDMFD (full descending)
FLDMDB<S/D/X>{cond} Rn!, <VFPregs>		synonym: FLDMEA (empty ascending)
FMSR{cond} Sn, Rd		Sn := Rd
FMRS{cond} Rd, Sn		Rd := Sn
FMSRR{cond} {Sn,Sm}, Rd, Rn		Sn := Rd, Sm := Rn
FMRRS{cond} Rd, Rn, {Sn,Sm}		Rd := Sn, Rn := Sm
FMDRR{cond} Dn, Rd, Rn		Dn[31:0] := Rd, Dn[63:32] := Rn
FMRRD{cond} Rd, Rn, Dn		Rd := Dn[31:0], Rn := Dn[63:32]
FMDLR{cond} Dn, Rd		Dn[31:0] := Rd
FMRDL{cond} Rd, Dn		Rd := Dn[31:0]
FMDHR{cond} Dn, Rd		Dn[63:32] := Rd
FMRDH{cond} Rd, Dn		Rd := Dn[63:32]
FMXR{cond} <VFPsysreg>, Rd		VFPsysreg := Rd
FMRX{cond} Rd, <VFPsysreg>		Rd := VFPsysreg
FMSTAT{cond}		CPSR flags := FPSCR flags