ARM CPU Project

Goals

• Implement an ARM v2a (ARM3) on a FPGA - Artix 7
• Useful completeness - Full data processing instruction set, maybe simplified in other areas
• Useful Performance - 25 MHz ARM3 or higher

Plan

• Start with emulation in software

Instruction set for ARM3

Programming model

After system reset, the ARM begins processing at address 0x0, with interrupts disabled and in SVC mode. This address is the location of the Reset Vector, which should be a branch to the reset code.

Modes

Mode                   Short  MM    Description                               Shadow registers
User mode              usr    0b00  Normal program execution, no privileges   None
Fast interrupt Request fiq    0b01  Fast interrupt handling                   R8 - R14
Interrupt request      irq    0b10  Normal interrupt handling                 R13, R14
Supervisor             svc    0b11  Privileged mode for the operating system  R13, R14

Hardware vectors

0x00  Reset                      B     branchThru0error
0x04  Undefined instruction      LDR   PC,UndHandler
0x08  SWI                        B     decodeSWI
0x0C  Prefetch abort             LDR   PC,PabHandler
0x10  Data abort                 LDR   PC,DabHandler
0x14  Address exception          LDR   PC,AexHandler
0x18  IRQ                        B     handleIRQ
0x1C  FIQ                        FIQ   code --> 0xFB

Registers

R0-R12
 General purpose
R13 (SP)
 General purpose, commonly used as stack pointer
R14 (LR)
 Link register, PC is copied to R14 by Branch-link instructions
 Can be used as general purpose if correctly saved and restored

R15 (PC)
 NZCVIFAAAAAAAAAAAAAAAAAAAAAAAAMM
31                              0

N Negative flag
Z Zero flag
C Carry flag
V Overflow flag
I Interrupt request disable
F Fast interrupt request disable
A Address bits, the 2 LSBs are always zero.
M Mode

The instruction set

<>     Optional.
(x|y)  Either x or y but not both.
#exp   Expression.
Rn     Register number(0-15).
shift  indicates one of the following:
       ASL (Rn|#exp)  Arithmetic shift left by contents of Rn or #exp
       LSL (Rn|#exp)  Logical shift left.
       ASR (Rn|#exp)  Arithmetic shift right.
       LSR (Rn|#exp)  Logical shift right.
       ROR (Rn|#exp)  Rotate right.
       RRX            Rotate right one bit with extend. LSB->C C->MSB
       ASL and LSL are the same, but LSL is preferred.
       #exp has a range of 0-31.

Condition codes

AL    Always                   This is the default
CC    Carry clear              C=0
CS    Carry set                C=1
EQ    Equal                    Z=1
GE    Greater than or equal    N=V
GT    Greater than             N=V and Z=0
HI    Higher (unsigned)        C=1 and Z=0
LE    Less than or equal       N<>V or Z=1
LS    Lower or same (unsigned) C=0  or Z=1
LT    Less than                N<>V
MI    Negative                 N=1
NE    Not equal                Z=0
NV    Never              **Do not use**, NOP = MOV R0,R0
PL    Positive                 N=0
VC    Overflow clear           V=0
VS    Overflow set             V=1
LO    Lower (unsigned)         same as CC
HS    Higher/same (unsigned)   same as CS

Arithmetic and bitwise instructions

opcode<cond><S> Rd,<Rn>,(#exp|Rm<,shift>)
#exp has a range of X ROR N*2  X=0-255 N=0-15

ADC  Add with carry                  Rd=Rn+Rm+C
ADD  Add                             Rd=Rn+Rm
SBC  Subtract with carry             Rd=Rn-Rm-(1-C)
SUB  Subtract                        Rd=Rn-Rm
RSC  Reverse subtract with carry     Rd=Rm-Rn-(1-C)
RSB  Reverse subtract                Rd=Rm-Rn
AND  Bitwise AND                     Rd=Rn AND Rm
BIC  Bitwise AND NOT                 Rd=Rn AND (NOT Rm)
ORR  Bitwise OR                      Rd=Rn OR Rm
EOR  Bitwise EOR                     Rd=Rn EOR Rm
MOV  Move                            Rd=Rm

Comparisons

opcode<cond><S|P> Rn,(#exp|Rm<,shift>)

CMN  Compare    Rn+Rm
CMP  Compare    Rn-Rm
TEQ  Test equal Rn EOR Rm
TST  Test       Rn AND Rm

"P" can set the PSR to a given value if in a privileged mode.
"S" is default behaviour

Multiply instructions

MUL<cond><S> Rd,Rm,Rs        Multiply             Rd=Rm*Rs
MLA<cond><S> Rd,Rm,Rs,Rn     Multiply-accumulate  Rd=Rm*Rs+Rn 

Integer multiplication returns 32LSB of product of two 32bit operands.
Rd must not be R15 or same as Rm. Timing is dependent of Rs.
If "S" is given, N and Z are set on the result, C and V are undefined.

Branching instructions

B<cond>  expression   Branch, PC+=expression
BL<cond> expression   Branch and link, R14=PC+4&PSR & PC+=expression

Single register/memory swap instruction (ARM3 or higher)

SWP<cond><B> Rdest,Rsrc,[Rbase]

Single register load/store instructions

LDR<cond><B><T> Rd,(address|#exp)    #exp has a range of +-4095 bytes.
STR<cond><B><T> Rd,(address|#exp)
"B" Byte transfer.
"T" Force address translation from a privileged mode. (Not pre-index!)

Address syntax

"!" update Rn after use  
pre-index                post-index
[Rn]
[Rn,#exp]<!>                [Rn],#exp
[Rn,<->Rm]<!>               [Rn],<->Rm
[Rn,<->Rm,shift #s]<!>      [Rn],<->Rm,shift #s

The PSR is never modified.
The PSR flags are not used if Rn=R15. (PC is 8 bytes ahead, pipelining!)
The PSR flags are used when the PC is used as Rm.

Multiple load/store instructions

LDM<cond>type Rn<!>,{Rlist}<^>
STM<cond>type Rn<!>,{Rlist}<^>
"!" update Rn after use 
For a load with R15 in the list "^" forces update of the PSR.
Otherwise "^" forces the load/store to access the User mode registers.
Rn is taken from the current bank, so update of Rn goes to the User bank.

Rlist is a list of register to transfer in a low to high order.

type
DA  Decrement Rn After    EA  Empty Ascending stack
DB  Decrement Rn Before   ED  Empty Descending stack
IA  Increment Rn After    FA  Full Ascending stack
IB  Increment Rn Before   FD  Full Descending stack

In an empty stack the stack pointer points to first free slot.
In a full stack the SP points to the last data item written to it.
An ascending stack grows from low to high memory addresses.
A descending stack grows from high to low memory addresses.

You can always load the base register(Rn).
Only if Rn is the lowest register then the original Rn is stored.
This will only have effect if you use "!".

If R15 is in the Rlist:
 The PSR is saved with the PC, the PC is 12 bytes ahead.
 The PSR is only loaded if you use "^", the mode decides what to update.

If R15 is used as Rn:
 The PSR is used as a part of the address!.
 Write back is switched off.

SWI instruction

SWI<cond> <expression>
Software interrupt used for system calls
Set the processor to SVC mode, and then the processor jumps to the reset vector at address 0x8.
The R14_svc will be corrupted if you execute a SWI in SVC mode.

Instruction set binary representation

Conditional execution

Instruction Bitmap                  No   Cond Code             Executes if:
0000xxxx xxxxxxxx xxxxxxxx xxxxxxxx 0    EQ(Equal)	        Z
0001xxxx xxxxxxxx xxxxxxxx xxxxxxxx 1    NE(Not Equal)	       ~Z
0010xxxx xxxxxxxx xxxxxxxx xxxxxxxx 2    CS(Carry Set)	        C
0011xxxx xxxxxxxx xxxxxxxx xxxxxxxx 3    CC(Carry Clear)      ~C

0100xxxx xxxxxxxx xxxxxxxx xxxxxxxx 4    MI(MInus)             N
0101xxxx xxxxxxxx xxxxxxxx xxxxxxxx 5    PL(PLus)             ~N
0110xxxx xxxxxxxx xxxxxxxx xxxxxxxx 6    VS(oVerflow Set)      V
0111xxxx xxxxxxxx xxxxxxxx xxxxxxxx 7    VC(oVerflow Clear)   ~V

1000xxxx xxxxxxxx xxxxxxxx xxxxxxxx 8    HI(HIgher)            C and ~Z
1001xxxx xxxxxxxx xxxxxxxx xxxxxxxx 9    LS(Lower or Same)    ~C and  Z
1010xxxx xxxxxxxx xxxxxxxx xxxxxxxx A    GE(Greater or equal)  N =  V
1011xxxx xxxxxxxx xxxxxxxx xxxxxxxx B    LT(Less Than)	        N = ~V

1100xxxx xxxxxxxx xxxxxxxx xxxxxxxx C    GT(Greater Than)     (N =  V) and ~Z
1101xxxx xxxxxxxx xxxxxxxx xxxxxxxx D    LE(Less or equal)    (N = ~V) or   Z
1110xxxx xxxxxxxx xxxxxxxx xxxxxxxx E    AL(Always)	        True
1111xxxx xxxxxxxx xxxxxxxx xxxxxxxx F    NV(Never)	        False

Data Processing Instructions

xxxx000 aaaa s nnnn dddd ccccc ttt mmmm  Register form    ADD Rd, Rn, Rm, ASL Rc
xxxx000 aaaa s nnnn dddd ccccc ttt mmmm  Register form    ADD Rd, Rn, Rm, ASL #c
xxxx000 1101 s 0000 dddd ccccc ttt mmmm  Register form    MOV Rd, Rm, ASL Rc ( n = 0 for move instructions )
xxxx001 aaaa s nnnn dddd rrrr bbbbbbbb   Immediate form   ADD Rd, Rn, #bbbbbbbb ROR #rrrr0
 
aaaa  Name Meaning              Operation                Condition codes
0000  AND  Boolean And          Rd = Rn AND Op2
0001  EOR  Boolean Eor          Rd = Rn EOR Op2
0010  SUB  Subtract             Rd = Rn - Op2
0011  RSB  Reverse Subtract     Rd = Op2 - Rn
0100  ADD  Addition             Rd = Rn + Op2
0101  ADC  Add with Carry       Rd = Rn + Op2 + C
0110  SBC  Subtract with carry  Rd = Rn - Op2 - (1 - C)
0111  RSC  Reverse sub w/carry  Rd = Op2 - Rn - (1 - C)
1000  TST  Test bit                  Rn AND Op2
1001  TEQ  Test equality             Rn EOR Op2
1010  CMP  Compare                   Rn - Op2
1011  CMN  Compare Negative          Rn + Op2
1100  ORR  Bitwise Or Register  Rd = Rn OR Op2
1101  MOV  Move value           Rd = Op2                 N and Z from Rd, if the shifter is used, C is set to be the last bit shifted out. 
1110  BIC  Bit clear            Rd = Rn AND NOT Op2
1111  MVN  Move Not             Rd = NOT Op2

ttt
000  LSL #c               Logical Shift Left
001  LSL Rc               Logical Shift Left
010  LSR #c for c != 0    Logical Shift Right
     LSR #32 for c  = 0
011  LSR Rc               Logical Shift Right
100  ASR #c for c != 0    Arithmetic Shift Right 
     ASR #32 for c  = 0
101  ASR Rc               Arithmetic Shift Right
110  ROR #c for c != 0    Rotate Right
     RRX    for c  = 0    Rotate Right one bit with extend
111  ROR Rc               Rotate Right