Difference between revisions of "A16 CPU"
From ScienceZero
| Line 1: | Line 1: | ||
[[image:A16schematic.png|right|thumb|A16 CPU]] | [[image:A16schematic.png|right|thumb|A16 CPU]] | ||
| + | [[image:A16emulator.png|right|thumb|A16 Emulator]] | ||
| + | |||
==A16 - High Performance 16 bit RISC CPU== | ==A16 - High Performance 16 bit RISC CPU== | ||
*Harvard style architecture that executes all instructions in a single clock cycle. | *Harvard style architecture that executes all instructions in a single clock cycle. | ||
Revision as of 19:41, 3 February 2007
A16 - High Performance 16 bit RISC CPU
- Harvard style architecture that executes all instructions in a single clock cycle.
- 8 registers, the program counter is mapped to register 8.
- Conditional execution of all instructions.
- Condition flags are set on demand.
- Branch-link instruction where the program counter is copied to R6.
