Difference between revisions of "A16 CPU"
From ScienceZero
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| − | [[image:A16schematic.png|right|thumb]] | + | [[image:A16schematic.png|right|thumb|A16 CPU]] |
| + | [[image:A16emulator.png|right|thumb|A16 Emulator]] | ||
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==A16 - High Performance 16 bit RISC CPU== | ==A16 - High Performance 16 bit RISC CPU== | ||
*Harvard style architecture that executes all instructions in a single clock cycle. | *Harvard style architecture that executes all instructions in a single clock cycle. | ||
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*Conditional execution of all instructions. | *Conditional execution of all instructions. | ||
*Condition flags are set on demand. | *Condition flags are set on demand. | ||
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*Branch-link instruction where the program counter is copied to R6. | *Branch-link instruction where the program counter is copied to R6. | ||
| − | [http://www.sciencezero.org | + | *[http://www.sciencezero.4hv.org/download/computing/a16%20emulator.zip Emulator and assembler - a16 emulator.zip (19 KB)] |
[[Category:computing]] | [[Category:computing]] | ||
Latest revision as of 23:18, 5 April 2022
A16 - High Performance 16 bit RISC CPU
- Harvard style architecture that executes all instructions in a single clock cycle.
- 8 registers, the program counter is mapped to register 8.
- Conditional execution of all instructions.
- Condition flags are set on demand.
- Branch-link instruction where the program counter is copied to R6.
