Difference between revisions of "A16 CPU"
From ScienceZero
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| − | [[image:A16schematic.png|right|thumb]] | + | [[image:A16schematic.png|right|thumb|A16 CPU]] |
==A16 - High Performance 16 bit RISC CPU== | ==A16 - High Performance 16 bit RISC CPU== | ||
*Harvard style architecture that executes all instructions in a single clock cycle. | *Harvard style architecture that executes all instructions in a single clock cycle. | ||
Revision as of 14:51, 3 February 2007
A16 - High Performance 16 bit RISC CPU
- Harvard style architecture that executes all instructions in a single clock cycle.
- 8 registers, the program counter is mapped to register 8.
- Conditional execution of all instructions.
- Condition flags are set on demand.
- All instructions execute in a single clock cycle.
- Branch-link instruction where the program counter is copied to R6.
